

`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:31:17 07/10/2013 
// Design Name: 
// Module Name:    spliter_tb 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module spliter_tb(
    );

    reg rst_n;
    reg clk;
    reg msg_end_1_2;
    reg valid_1_2;
    wire [7:0] data_1_2;
    wire [7:0] data_2_3;
    wire [49:0] sel_2_3;
    reg [7:0] data_test [0:100];
    
    wire [3:0] field_counter_2_3;
    integer counter;
    wire valid_2_3;
    wire msg_end_2_3;

    initial
    begin
        $readmemh("test_data.txt",data_test);
        counter=0;
        rst_n=0;
        clk=0;
        msg_end_1_2=0;
        valid_1_2=0;
        #12
        rst_n=1;
        valid_1_2=1;
        #90
        msg_end_1_2=1;
        #10
        msg_end_1_2=0;
    end
    
    always #5 clk=~clk;
    
    always @(posedge clk)
    begin
        if(rst_n&valid_1_2)
            counter <= counter+1;
    end
    assign data_1_2=data_test[counter];

    field_spliter fp_test(
        .rst_n(rst_n),
        .clk(clk),
        .valid_1_2(valid_1_2),
        .data_1_2(data_1_2),
        .msg_end_1_2(msg_end_1_2),
        .valid_2_3(valid_2_3),
        .data_2_3(data_2_3),
        .sel_2_3(sel_2_3),
        .field_counter_2_3(field_counter_2_3),
        .msg_end_2_3(msg_end_2_3)
    );

endmodule
